US 11,900,116 B1
Loosely-coupled slice target file data
Dung Q. Nguyen, Austin, TX (US); Brian W. Thompto, Austin, TX (US); Jose E. Moreira, Irvington, NY (US); Jessica Hui-Chun Tseng, Fremont, CA (US); Pratap C. Pattnaik, Yorktown Heights, NY (US); Kattamuri Ekanadham, Mohegan Lake, NY (US); and Manoj Kumar, Yorktown Heights, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 29, 2021, as Appl. No. 17/489,746.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30109 (2013.01); G06F 9/3836 (2013.01); G06F 9/3869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory, and
a processor in communication with the memory, the processor being configured to perform processes comprising:
determining that two instructions may be combined based on a processing power of the processor and a size of the instructions;
fusing the two instructions into a pair;
mapping the two instructions with a single register tag;
writing the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions;
writing the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions;
writing the fused instruction pair into an issue queue;
issuing the fused instruction pair to a vector-scalar transformation units (VSU); and
executing the two instructions.