CPC G06F 9/30036 (2013.01) [G06F 9/30101 (2013.01)] | 30 Claims |
1. A device comprising:
a vector register file including a plurality of vector registers comprising a set of source vector registers and a first permutation result register, wherein the set of source vector registers has a set count and the source vector registers contain source data for a permutation instruction that includes multiple parameters;
a memory configured to store the permutation instruction, wherein one or two of the multiple parameters are register selection order parameters that characterize a register selection order, wherein each of the register selection order parameters is a scalar value, wherein one of the register selection order parameters is a periodicity parameter indicating the set count of the set of source vector registers, wherein the register selection order indicates a repeated pattern of register selection, wherein the periodicity parameter indicates a length of the repeated pattern, and wherein a particular source vector register is included once during each iteration of the repeated pattern; and
a processor configured to execute the permutation instruction to, for each particular element of multiple elements of the first permutation result register of the plurality of vector registers:
select, based on the register selection order, a source vector register of the plurality of vector registers; and
populate the particular element based on a value in a corresponding element of the selected source vector register.
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