US 11,900,108 B2
Rotate instructions that complete execution either without writing or reading flags
Vinodh Gopal, Westborough, MA (US); James D. Guilford, Northborough, MA (US); Gilbert M. Wolrich, Framingham, MA (US); Wajdi K. Feghali, Boston, MA (US); Erdinc Ozturk, Hillsboro, OR (US); Martin G. Dixon, Portland, OR (US); Sean P. Mirkes, Beaverton, OR (US); Bret L. Toll, Hillsboro, OR (US); Maxim Loktyukhin, Folsom, CA (US); Mark C. Davis, Portland, OR (US); and Alexandre J. Farcy, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 30, 2021, as Appl. No. 17/461,949.
Application 17/461,949 is a continuation of application No. 15/939,693, filed on Mar. 29, 2018, granted, now 11,106,461.
Application 15/939,693 is a continuation of application No. 14/562,310, filed on Dec. 5, 2014, granted, now 9,940,131, issued on Apr. 10, 2018.
Application 14/562,310 is a continuation of application No. 13/947,958, filed on Jul. 22, 2013, granted, now 9,164,762, issued on Oct. 20, 2015.
Application 13/947,958 is a continuation of application No. 12/655,213, filed on Dec. 26, 2009, granted, now 8,504,807, issued on Aug. 6, 2013.
Prior Publication US 2022/0107806 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30032 (2013.01) [G06F 9/30094 (2013.01); G06F 9/30098 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a register to store a plurality of flags, including a carry flag, a sign flag, a zero flag, and an overflow flag;
a decoder to decode instructions, including a single rotate right instruction, wherein some of the instructions indicate 64-bit general-purpose registers that are to store 64-bit operands in a 64-bit mode and are to store 32-bit operands in a 32-bit mode, wherein the 32-bit operands are to be stored in a lower 32-bits of the 64-bit general-purpose registers, and wherein the single rotate right instruction is to indicate a 64-bit operand size, a first 64-bit source operand, a second 64-bit source operand, and has a field to specify a first 64-bit general-purpose register; and
execution circuitry coupled with the decoder, the execution circuitry to perform operations corresponding to the single rotate right instruction, including to:
rotate the first 64-bit source operand right by an amount that is to be indicated by the second 64-bit source operand, wherein bits rotated out of a least significant bit of the first 64-bit source operand are to be rotated into a most significant bit of the first 64-bit source operand;
store a result that is to include the first 64-bit source operand rotated right by the amount into the first 64-bit general-purpose register; and
complete the execution of the single rotate right instruction without causing the carry flag to be read, without causing the carry flag to be written, without causing the sign flag to be read, without causing the sign flag to be written, without causing the zero flag to be read, without causing the zero flag to be written, without causing the overflow flag to be read, and without causing the overflow flag to be written.