US 11,900,043 B2
Electronic device for manufacturing semiconductor device and operating method of electronic device
Sooyong Lee, Yongin-si (KR); Dongho Kim, Hwaseong-si (KR); Sangwook Kim, Yongin-si (KR); Jungmin Kim, Hwaseong-si (KR); Seunghune Yang, Seoul (KR); Jeeyong Lee, Anyang-si (KR); Changmook Yim, Hwaseong-si (KR); and Yangwoo Heo, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 22, 2022, as Appl. No. 17/701,520.
Claims priority of application No. 10-2021-0097066 (KR), filed on Jul. 23, 2021.
Prior Publication US 2023/0028712 A1, Jan. 26, 2023
Int. Cl. G06F 30/30 (2020.01); G03F 7/00 (2006.01); G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/27 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/398 (2020.01) [G03F 7/705 (2013.01); G03F 7/70441 (2013.01); G06F 30/27 (2020.01); G06F 30/392 (2020.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
10. An operating method of an electronic device for manufacturing a semiconductor device, the method comprising:
receiving a design layout and an after cleaning inspection (ACI) layout corresponding to the design layout;
measuring at least one of a bias(s), a critical dimension (CD), or a mis-align between the design layout and the after cleaning inspection layout;
tagging features on the after cleaning inspection layout; and
performing learning on a process proximity correction module based on the tagged features and at least one of the bias(s), the critical dimension, or the mis-align.