US 11,900,037 B2
Circuit synthesis optimization for implements on integrated circuit
Chao-Chun Lo, Hsinchu (TW); Boh-Yi Huang, San Jose, CA (US); Chih-yuan Stephen Yu, San Jose, CA (US); Yi-Lin Chuang, Taipei (TW); and Chih-Sheng Hou, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 24, 2022, as Appl. No. 17/752,333.
Application 17/752,333 is a continuation of application No. 17/075,760, filed on Oct. 21, 2020, granted, now 11,347,920.
Prior Publication US 2022/0284162 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/30 (2020.01); G06F 30/337 (2020.01); G06F 30/392 (2020.01); G06F 30/31 (2020.01); G06F 30/3308 (2020.01); G06F 30/327 (2020.01); G06F 119/08 (2020.01); G06F 119/18 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/337 (2020.01) [G06F 30/31 (2020.01); G06F 30/327 (2020.01); G06F 30/3308 (2020.01); G06F 30/392 (2020.01); G06F 2119/06 (2020.01); G06F 2119/08 (2020.01); G06F 2119/12 (2020.01); G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
15. A non-transitory computer-readable medium encoded with memory storing instructions for fabricating an integrated circuit, which when executed result in operations comprising:
receiving a circuit design;
generating a floor plan of the circuit design;
accessing the floor plan and creating a physically simulated circuit using the floor plan; and
sweeping over a range of operating conditions to analyze power, performance, and area of the physically simulated circuit.