US 11,900,035 B2
Attribute-point-based timing constraint formal verification
Chao-Chun Lo, Hsinchu (TW); Boh-Yi Huang, San Jose, CA (US); and Chih-yuan Stephen Yu, San Jose, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 1, 2023, as Appl. No. 18/176,717.
Application 18/176,717 is a division of application No. 17/020,948, filed on Sep. 15, 2020, granted, now 11,620,423.
Prior Publication US 2023/0205958 A1, Jun. 29, 2023
Int. Cl. G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 119/16 (2020.01); G06F 119/12 (2020.01); G06F 111/04 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 2111/04 (2020.01); G06F 2119/12 (2020.01); G06F 2119/16 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a target circuit design;
determining an attribute mismatch between the target circuit design and a golden circuit design by:
determining whether a log for synthesis design constraints associated with the golden circuit design contains an error, wherein the target circuit design has a different technology node size than the golden circuit design;
evaluating a target attribute of the target circuit design and a golden attribute of the golden circuit design; and
determining whether a number of timing paths of the target circuit design and a number of timing paths of the golden circuit design are equivalent; and
providing the attribute mismatch for further design iterations, wherein at least one of the operations is performed by at least one data processor.