US 11,899,967 B2
Vector processor data storage
Nicholas Moore, Boston, MA (US); Gongyu Wang, Newton, MA (US); Bradley Dobbie, Medford, MA (US); Tyler J. Kenney, Boston, MA (US); and Ayon Basumallik, Framingham, MA (US)
Assigned to Lightmatter, Inc., Boston, MA (US)
Filed by Lightmatter, Inc., Boston, MA (US)
Filed on Nov. 15, 2021, as Appl. No. 17/527,107.
Claims priority of provisional application 63/114,373, filed on Nov. 16, 2020.
Prior Publication US 2022/0155996 A1, May 19, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 15/80 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 15/8061 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a vector processor configured to:
receive as an input one of a first vector and a second vector,
provide as an output, based at least in part on the input, the other one of the first vector and the second vector wherein the second vector is longer than the first vector and
split the second vector into a plurality of stripes; and
one or more computer memory units implementing a buffer comprising a plurality of lines, configured to store the second vector in the plurality of stripes, wherein a first stripe of the plurality of stripes and a second stripe of the plurality of stripes are aligned in the buffer on separate lines of the plurality of lines.