US 11,899,966 B2
Implementing fault tolerant page stripes on low density memory systems
Kishore Kumar Muchherla, San Jose, CA (US); Mark A. Helm, Santa Cruz, CA (US); Giuseppina Puzzilli, Boise, ID (US); Peter Feeley, Boise, ID (US); Yifen Liu, Boise, ID (US); Violante Moschiano, Avezzano (IT); Akira Goda, Tokyo (JP); and Sampath K. Ratnam, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 25, 2022, as Appl. No. 17/872,206.
Application 17/872,206 is a continuation of application No. 17/079,048, filed on Oct. 23, 2020, granted, now 11,449,271.
Claims priority of provisional application 62/955,034, filed on Dec. 30, 2019.
Prior Publication US 2022/0357873 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations, comprising:
receiving a host data item;
storing the host data item in a first page of the memory device, wherein the first page is associated with a fault tolerant stripe, and wherein the first page is separated from a second page of the fault tolerant stripe by one or more wordlines including a deck separation wordline, wherein the first page and the second page have sequential page numbers; and
storing, on the memory device, redundancy metadata associated with the fault tolerant stripe.