US 11,899,961 B2
Redundant computing across planes
Sean S. Eilert, Penryn, CA (US); Kenneth M. Curewitz, Cameron Park, CA (US); Helena Caminal, Ithaca, NY (US); and Ameen D. Akel, Rancho Cordova, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 23, 2022, as Appl. No. 17/652,229.
Claims priority of provisional application 63/266,216, filed on Dec. 30, 2021.
Prior Publication US 2023/0214148 A1, Jul. 6, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 32 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory die comprising a plurality of planes arranged in a plurality of tiles, of the plurality of planes comprising content-addressable memory cells; and
logic coupled with the memory die and configured to:
perform a computational operation on first data that is stored in a first plane of the plurality of planes, wherein the computational operation is based at least in part on a capability of the content-addressable memory cells, and wherein the first data is representative of a set of contiguous bits of a vector;
perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane of the plurality of planes, wherein the second data is representative of the set of contiguous bits of the vector; and
read, from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.