US 11,899,959 B2
Method of testing memory device, memory built-in self test (MBIST) circuit, and memory device for reducing test time
Jaewon Park, Hwaseong-si (KR); Sangkil Park, Hwaseong-si (KR); and Jaehoon Lee, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 3, 2021, as Appl. No. 17/337,992.
Claims priority of application No. 10-2020-0131968 (KR), filed on Oct. 13, 2020.
Prior Publication US 2022/0113889 A1, Apr. 14, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0653 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of testing a memory device including a plurality of memory banks and a memory built-in self-test (MBIST) circuit, wherein the plurality of memory banks include a plurality of memory cells, and the MBIST circuit performs a double data rate (DDR) test or a parallel bit test (PBT), the method comprising:
setting an MBIST option, the MBIST option comprises a DDR test mode and a PBT test mode;
based on the PBT test mode being set as the MBIST option, performing the PBT test on the plurality of memory banks;
based on the DDR test mode being set as the MBIST option, performing the DDR test on one bank selected from among the plurality of memory banks;
based on detecting a defective cell as a result of the DDR test or the PBT test, performing a repair operation for repairing the defective cell with a redundancy cell through the MBIST circuit; and
performing a re-test for verifying the repair operation through the MBIST circuit, wherein the re-test is performed on one or more memory cells including the defective cell among the plurality of memory cells.