US 11,899,948 B2
Performance control for a memory sub-system
Yun Li, Fremont, CA (US); James P. Crowley, Longmont, CO (US); Jiangang Wu, Milpitas, CA (US); and Peng Xu, Milpitas, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 9, 2022, as Appl. No. 17/984,118.
Application 17/984,118 is a continuation of application No. 16/731,936, filed on Dec. 31, 2019, granted, now 11,520,502.
Prior Publication US 2023/0071878 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0631 (2013.01) [G06F 3/061 (2013.01); G06F 3/0653 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
monitoring a bandwidth of a backend of a memory sub-system for writing data to a memory device;
determining that the bandwidth of the backend satisfies one or more performance criteria that are based at least in part on performance between the memory sub-system and a host system that is external to the memory sub-system; and
allocating a quantity of one or more slots of a buffer to a frontend of the memory sub-system based at least in part on determining that the bandwidth of the backend satisfies the one or more performance criteria.