US 11,899,938 B2
Techniques to reduce write amplification
Yanhua Bi, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/283,499
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Dec. 7, 2020, PCT No. PCT/CN2020/134236
§ 371(c)(1), (2) Date Apr. 7, 2021,
PCT Pub. No. WO2022/120517, PCT Pub. Date Jun. 16, 2022.
Prior Publication US 2022/0404976 A1, Dec. 22, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 2212/7204 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array; and
a controller coupled with the memory array and configured to cause the apparatus to:
receive a write command from a host device;
determine whether a quantity of commands stored in a buffer for execution by the memory array satisfies a first threshold;
if the quantity of commands stored in the buffer fails to satisfy the first threshold, determine a ratio of a total quantity of data written to the memory array to a quantity of data requested to be written to the memory array by the host device; and
write data associated with the write command to the memory array using a first mode to write data or a second mode to write data,
wherein the data is written using the first mode based at least in part on the quantity of commands satisfying the first threshold or the ratio failing to satisfy a second threshold, and
wherein the data is written using the second mode based at least in part on the quantity of commands failing to satisfy the first threshold and the ratio satisfying the second threshold.