US 11,899,741 B2
Memory device and method
Hyung-Dal Kwon, Hwaseong-si (KR); and Seung Wook Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 23, 2020, as Appl. No. 16/856,380.
Claims priority of application No. 10-2019-0115443 (KR), filed on Sep. 19, 2019.
Prior Publication US 2021/0089610 A1, Mar. 25, 2021
Int. Cl. G06F 17/15 (2006.01); G06F 7/544 (2006.01); G06F 17/14 (2006.01); G06F 17/16 (2006.01); G06F 13/28 (2006.01); H03H 17/02 (2006.01)
CPC G06F 17/15 (2013.01) [G06F 7/5443 (2013.01); G06F 13/28 (2013.01); G06F 17/14 (2013.01); G06F 17/16 (2013.01); H03H 17/0213 (2013.01)] 36 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory configured to store input data and filter data for a convolution operation; and
a function processor, embedded inside the memory device, configured to:
in response to a read command of at least a portion of data from among the input data and the filter data, transform at least a first portion of the input data using a first transforming matrix and transform at least a second portion of the filter data using a second transforming matrix, respectively during a clock cycle corresponding to the read command, the first transforming matrix and the second transforming matrix being respectively based on a parameter of the convolution operation, and output a corresponding transformation result, as transformed data, using a third transforming matrix; and
reduce information loss associated with the outputting by adjusting relationship between the second transforming matrix and the third transforming matrix.