US 11,899,615 B2
Multiple dies hardware processors and methods
Nevine Nassif, Arlington, MA (US); Yen-Cheng Liu, Portland, OR (US); Krishnakanth V. Sistla, Portland, OR (US); Gerald Pasdast, San Jose, CA (US); Siva Soumya Eachempati, Campbell, CA (US); Tejpal Singh, Hudson, MA (US); Ankush Varma, Portland, OR (US); Mahesh K. Kumashikar, Bangalore (IN); Srikanth Nimmagadda, Bangalore (IN); Carleton L. Molnar, Northborough, MA (US); Vedaraman Geetha, Fremont, CA (US); Jeffrey D. Chamberlain, Tracy, CA (US); William R. Halleck, Lancaster, MA (US); George Z Chrysos, Portland, OR (US); John R. Ayers, Portland, OR (US); and Dheeraj R. Subbareddy, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 27, 2023, as Appl. No. 18/102,568.
Application 18/102,568 is a continuation of application No. 17/513,795, filed on Oct. 28, 2021, granted, now 11,586,579.
Application 17/513,795 is a continuation of application No. 16/917,888, filed on Jun. 30, 2020, granted, now 11,294,852, issued on Apr. 5, 2022.
Application 16/917,888 is a continuation of application No. 15/721,822, filed on Sep. 30, 2017, granted, now 10,795,853, issued on Oct. 6, 2020.
Claims priority of provisional application 62/406,362, filed on Oct. 10, 2016.
Prior Publication US 2023/0169032 A1, Jun. 1, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 15/78 (2006.01); G06F 1/10 (2006.01); G06F 15/167 (2006.01); G06F 1/04 (2006.01); G06F 1/12 (2006.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 15/173 (2006.01)
CPC G06F 15/7889 (2013.01) [G06F 1/04 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); G06F 9/3869 (2013.01); G06F 9/5038 (2013.01); G06F 15/167 (2013.01); G06F 15/17312 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of dies including a first die and a plurality of other dies;
a plurality of secondary management controllers, each secondary management controller integral to a corresponding one of the plurality of other dies;
an interconnect coupled to the plurality of dies; and
a primary management controller integral to the first die to transmit one or more management requests to the plurality of secondary management controllers over the interconnect, the plurality of secondary management controllers to perform a modification to a clock of the corresponding one of the plurality of other dies based, at least in part, on the one or more management requests.