US 11,899,614 B2
Instruction based control of memory attributes
Joydeep Ray, Folsom, CA (US); Altug Koker, El Dorado Hills, CA (US); Varghese George, Folsom, CA (US); Mike Macpherson, Portland, OR (US); Aravindh Anantaraman, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Nicolas Galoppo von Borries, Portland, OR (US); and Ben J. Ashbaugh, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2022, as Appl. No. 17/849,201.
Application 17/849,201 is a continuation of application No. 17/428,530, filed on Aug. 4, 2021.
Claims priority of provisional application 62/819,361, filed on Mar. 15, 2019.
Claims priority of provisional application 62/819,337, filed on Mar. 15, 2019.
Claims priority of provisional application 62/819,435, filed on Mar. 15, 2019.
Prior Publication US 2023/0014565 A1, Jan. 19, 2023
Int. Cl. G06F 15/78 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 17/18 (2006.01); G06F 12/0802 (2016.01); G06F 7/544 (2006.01); G06F 7/575 (2006.01); G06F 12/02 (2006.01); G06F 12/0866 (2016.01); G06F 12/0875 (2016.01); G06F 12/0895 (2016.01); G06F 12/128 (2016.01); G06F 12/06 (2006.01); G06F 12/1009 (2016.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); H03M 7/46 (2006.01); G06F 12/0811 (2016.01); G06F 15/80 (2006.01); G06F 17/16 (2006.01); G06F 7/58 (2006.01); G06F 12/0871 (2016.01); G06F 12/0862 (2016.01); G06F 12/0897 (2016.01); G06F 9/50 (2006.01); G06F 12/0804 (2016.01); G06F 12/0882 (2016.01); G06F 12/0891 (2016.01); G06F 12/0893 (2016.01); G06F 12/0888 (2016.01); G06T 15/06 (2011.01); G06N 3/08 (2023.01)
CPC G06F 15/7839 (2013.01) [G06F 7/5443 (2013.01); G06F 7/575 (2013.01); G06F 7/588 (2013.01); G06F 9/3001 (2013.01); G06F 9/3004 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30065 (2013.01); G06F 9/30079 (2013.01); G06F 9/3887 (2013.01); G06F 9/5011 (2013.01); G06F 9/5077 (2013.01); G06F 12/0215 (2013.01); G06F 12/0238 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 12/0802 (2013.01); G06F 12/0804 (2013.01); G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 12/0866 (2013.01); G06F 12/0871 (2013.01); G06F 12/0875 (2013.01); G06F 12/0882 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/0893 (2013.01); G06F 12/0895 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 12/128 (2013.01); G06F 15/8046 (2013.01); G06F 17/16 (2013.01); G06F 17/18 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); H03M 7/46 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/3867 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/302 (2013.01); G06F 2212/401 (2013.01); G06F 2212/455 (2013.01); G06F 2212/60 (2013.01); G06N 3/08 (2013.01); G06T 15/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processor comprising:
a processing resource including a graphics engine;
a memory device;
a first cache coupled with the processing resource and the memory device; and
circuitry to process a memory access message received from the processing resource, the memory access message to access data of the memory device on behalf of the graphics engine, wherein to process the memory access message, the circuitry is configured to:
determine whether the memory access message includes a first cache attribute, the first cache attribute to indicate whether the data is cacheable within the first cache;
determine whether state information associated with the data includes a second cache attribute, the second cache attribute to indicate whether the data is cacheable within the first cache;
arbitrate between the first cache attribute and the second cache attribute according to presence or absence of the first cache attribute and the second cache attribute and respective priorities associated with the first cache attribute and the second cache attribute; and
transmit a memory access request to the first cache, the memory access request including arbitrated cache attributes.