US 11,899,613 B1
Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging
Amrita Mathuriya, Portland, OR (US); Christopher B. Wilkerson, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Debo Olaosebikan, San Francisco, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Aug. 20, 2021, as Appl. No. 17/408,251.
Application 17/408,251 is a continuation of application No. 17/396,585, filed on Aug. 6, 2021.
Int. Cl. G06F 15/78 (2006.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 9/50 (2006.01)
CPC G06F 15/7825 (2013.01) [G06F 9/4881 (2013.01); G06F 9/5027 (2013.01); G06F 9/54 (2013.01); G06F 15/7821 (2013.01); G06F 15/7842 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor core coupled to an accelerator core via an interconnect; and
a first memory coupled to the processor core, wherein the accelerator core is coupled to a second memory, wherein the processor core is to fetch an instruction and to determine whether the instruction is to be scheduled for processing by the processor core of a compute die or the accelerator core of an accelerator die based on a type of the instruction, wherein the processor core is to assemble the instruction in a command packet that includes data address associated with the second memory, and to send the command packet to the accelerator core via the interconnect, and wherein the processor core and/or the accelerator core includes ferroelectric logic.