US 11,899,590 B2
Intelligent cache with read destructive memory cells
Jon D. Trantham, Chanhassen, MN (US); Praveen Viraraghavan, Chicago, IL (US); John W. Dykes, Eden Prairie, MN (US); Ian J. Gilbert, Chanhassen, MN (US); Sangita Shreedharan Kalarickal, Eden Prairie, MN (US); Matthew J. Totin, Excelsior, MN (US); Mohamad El-Batal, Superior, CO (US); and Darshana H. Mehta, Shakopee, MN (US)
Assigned to SEAGATE TECHNOLOGY LLC, Fremont, CA (US)
Filed by Seagate Technology LLC, Fremont, CA (US)
Filed on Jun. 20, 2022, as Appl. No. 17/844,141.
Claims priority of provisional application 63/212,403, filed on Jun. 18, 2021.
Prior Publication US 2022/0405208 A1, Dec. 22, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0891 (2016.01); G06F 12/0895 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0895 (2013.01); G06F 12/1027 (2013.01); G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a cache consisting of read destructive memory cells;
a map connected to the first cache, the map consisting of read destructive memory cells storing information about data resident in the first cache; and
a controller connected to the first cache and map, the controller configured to output less than an entirety of the data stored in the first cache in response to a map hit by a host data request, the entirety of the first cache and map subsequently filled with different data identified by the controller.