CPC G06F 12/0246 (2013.01) [G06F 3/0679 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/7207 (2013.01); G06F 2212/7208 (2013.01); G06F 2212/7211 (2013.01); G11C 16/102 (2013.01)] | 22 Claims |
1. A storage device comprising:
an interface to receive data access requests from a host device; and
flash memory comprising erase units;
wherein the storage device further comprises logic to cause the storage device to:
issue commands to the flash memory responsive to the data access requests received from the host device via the interface;
update metadata for one or more respective subdivisions of addressable memory space, each of the one or more respective subdivisions corresponding to a mutually-exclusive subset of one or more of the erase units, wherein each of the subdivisions is associated with a size and a respective logical address, the metadata representing
an extent to which the respective subdivisions are full, and
a time associated with the respective subdivisions;
receive one or more requests from the host device and responsively transmit, to the host device, based on the metadata
information identifying the size and the logical address of a specific subdivision of the one or more respective subdivisions of addressable memory space,
information representing the extent to which the specific subdivision is full, and
information representing the time associated with the specific subdivision; and
receive a write request from the host device, wherein the write request specifies the logical address of the specific subdivision, and responsively store write data in at least one of the one or more erase units of the mutually-exclusive subset corresponding to the specific subdivision; and
wherein each said logic comprises at least one of hardware circuitry or instructions stored on non-transitory machine-readable media that are to control the function of hardware circuitry.
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