US 11,899,574 B2
L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches
Xiangang Luo, Fremont, CA (US); and Qing Liang, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 13, 2022, as Appl. No. 17/965,542.
Application 17/965,542 is a continuation of application No. 16/586,519, filed on Sep. 27, 2019, granted, now 11,487,653.
Prior Publication US 2023/0031365 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01); G06F 12/0804 (2016.01); G06F 12/0873 (2016.01); G06F 12/1045 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 12/0804 (2013.01); G06F 12/0873 (2013.01); G06F 12/1054 (2013.01); G06F 13/1668 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a controller, configured to perform operations comprising:
receive a write request;
responsive to receiving the write request, compare an amount of data to be written in the write request to a threshold amount of data;
responsive to a determination that the amount of data to be written in the write request exceeds the threshold amount of data, storing a mapping between a physical and logical address corresponding to the write request in a first cache, the first cache configured to store, in a volatile memory, contiguous portions of a logical-to-physical mapping table indexed by logical block address;
responsive to a determination that the amount of data to be written in the write request does not exceed the threshold amount of data, storing the mapping in a second cache, the second cache configured to store, in a volatile memory, non-contiguous portions of the logical-to-physical mapping table indexed by logical block address;
determine if the second cache is full; and
in response to a determination that the second cache is full:
determine if a first logical block address of the second cache is present in the first cache;
in response to a determination that the first logical block address of the second cache is present in the first cache:
store a first physical address associated with the first logical block address of the second cache with the first logical block address in the first cache; and
mark a record with the first logical block address in the second cache as invalid.