US 11,899,564 B2
Debug apparatus and recording medium
Tomoyoshi Ujii, Tokyo (JP); Yuki Mori, Tokyo (JP); and Kazunori Ochiai, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed on May 19, 2022, as Appl. No. 17/748,738.
Prior Publication US 2023/0376402 A1, Nov. 23, 2023
Int. Cl. G06F 11/36 (2006.01); G06F 1/20 (2006.01)
CPC G06F 11/366 (2013.01) [G06F 1/206 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A debug apparatus for debugging target programs including a plurality of programs operating in a semiconductor device including a plurality of Central Processing Units (CPUs) and a plurality of temperature sensors, the debug apparatus comprising:
a processor; and
a memory configured to store a control program, CPU position information, temperature sensor position information, CPU type information, and target program constraint information,
wherein the plurality of CPUs is configured to execute the target programs,
wherein, while the target programs are executed by the plurality of CPUs, the plurality of temperature sensors is configured to measure temperature of the semiconductor device,
wherein the CPU position information comprises information for identifying a position of the plurality of CPUs in the semiconductor device,
wherein the temperature sensors position information comprises information for identifying a position of the plurality of temperature sensors in the semiconductor device,
wherein the CPU type information comprises information for identifying a type of the plurality of CPUs,
wherein the target program constraint information comprises information used in determining whether to change allocation of the target programs executed by the plurality of CPUs,
wherein, when executed by the processor, the control program causes the debug apparatus to:
instruct the semiconductor device to execute the target programs;
acquire a plurality of temperature data measured by the plurality of temperature sensors;
determine, from the plurality of CPUs, at least one CPU where a number of target programs executed is to be decreased, as a first change target CPU and at least one CPU where the number of target programs executed is to be increased, as a second change target CPU, based on the plurality of temperature data, the CPU position information, and the temperature sensor position information; and
change the allocation of the target programs executed by the plurality of CPUs based on the first change target CPU, the second change target CPU, the CPU type information, and the target program constraint information.