US 11,899,550 B2
Enhanced auxiliary memory mapped interface test systems and methods
Chi Yuan, San Jose, CA (US); and Srdjan Malisic, San Jose, CA (US)
Assigned to Advantest Corporation, Tokyo (JP)
Filed by Advantest Corporation, Tokyo (JP)
Filed on Jan. 28, 2021, as Appl. No. 17/161,417.
Claims priority of provisional application 63/003,013, filed on Mar. 31, 2020.
Prior Publication US 2021/0303430 A1, Sep. 30, 2021
Int. Cl. G06F 11/273 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01)
CPC G06F 11/2733 (2013.01) [G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An enhanced auxiliary interface test system comprises:
a load board configured to couple with a plurality of devices under test (DUTs);
testing electronics configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board;
a controller configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics; and
a memory mapped interface configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel, wherein the memory mapped interface is supported by modifications to a field programmable gate array (FPGA), a driver, and a user space.