US 11,899,532 B2
Determining locations in NAND memory for boot-up code
Nitul Gohain, Bangalore (IN); Giuseppe Cariello, Boise, ID (US); and Jameer Mulani, Bangalore (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 31, 2022, as Appl. No. 17/804,826.
Prior Publication US 2023/0393934 A1, Dec. 7, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0632 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/076 (2013.01); G06F 11/0757 (2013.01); G06F 11/0772 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device comprising a plurality of memory cells, and
one or more controllers coupled with the memory device and configured to cause the apparatus to:
receive an indication of a timeout duration for a boot sequence of a host system;
determine a quantity of bits configured to be output by respective memory cells of a set of memory cells of the plurality of memory cells;
select, based at least in part on the timeout duration, the set of memory cells based at least in part on the quantity of bits being less than a data level threshold;
store information for the boot sequence in the set of memory cells based at least in part on selecting the set of memory cells; and
access the information for the boot sequence that is stored in the set of memory cells based at least in part on an initialization of the boot sequence.