US 11,899,518 B2
Analog MAC aware DNN improvement
Gilad Kirshenboim, Petach Tiqva (IL); Ran Sahar, Evan Yehuda (IL); Douglas C. Burger, Bellevue, WA (US); and Yehonathan Refael Kalim, Herzeliya (IL)
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/551,875.
Prior Publication US 2023/0185352 A1, Jun. 15, 2023
Int. Cl. G06F 1/3234 (2019.01); G06F 7/544 (2006.01); G06F 13/10 (2006.01); G06N 3/02 (2006.01)
CPC G06F 1/3234 (2013.01) [G06F 7/5443 (2013.01); G06F 13/102 (2013.01); G06N 3/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural processing unit (NPU) configured to implement an artificial intelligence (AI) neural network (NN) model, the NPU comprising:
a multiply and accumulate (MAC) circuit comprising:
a plurality of MAC processing elements (PEs) comprising:
a multiplier configured to perform multiplication operations on inputs and weights to generate mid-term values; and
an accumulator configured to accumulate the mid-term values as an analog output;
an analog to digital converter (ADC) configured to convert the analog output to a digital output;
a memory storing bit precision information determined during at least one of training or quantization of the AI NN model;
a precision determiner configured to dynamically determine a precision indication based on the bit precision information; and
a power conservation controller configured to selectively vary a precision of the digital output, thereby reducing power consumption of the MAC circuit, the power conservation controller configured to receive the precision indication and selectively vary the precision of the digital output based on the precision indication.