US 11,899,367 B2
Dummy insertion for improving throughput of electron beam lithography
Shih-Ming Chang, Hsinchu (TW); Wen Lo, Taipei (TW); Chun-Hung Liu, Kaohsiung (TW); Chia-Hua Chang, New Taipei (TW); Hsin-Wei Wu, Hsinchu (TW); Ta-Wei Ou, Taichung (TW); Chien-Chih Chen, Tainan (TW); and Chien-Cheng Chen, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Dec. 12, 2022, as Appl. No. 18/064,548.
Application 18/064,548 is a continuation of application No. 17/366,319, filed on Jul. 2, 2021, granted, now 11,526,081.
Application 17/366,319 is a continuation of application No. 16/138,402, filed on Sep. 21, 2018, granted, now 11,054,748, issued on Jul. 6, 2021.
Prior Publication US 2023/0273524 A1, Aug. 31, 2023
Int. Cl. G03F 7/20 (2006.01); G03F 1/36 (2012.01); G03F 1/78 (2012.01)
CPC G03F 7/2061 (2013.01) [G03F 1/36 (2013.01); G03F 1/78 (2013.01)] 20 Claims
 
1. An electron beam lithography system comprising:
a processor; and
a non-transitory computer-readable medium having stored thereon computer-readable instructions, wherein the computer-readable instructions are executable by the processor to cause the electron beam lithography system to perform operations that include:
receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout, and
inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout, wherein the electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.