US 11,899,320 B2
Array substrate and liquid crystal display panel
Hongpeng Li, Beijing (CN); Pengxia Liang, Beijing (CN); Zheng Fang, Beijing (CN); Ge Shi, Beijing (CN); Hyunsic Choi, Beijing (CN); Yanliu Sun, Beijing (CN); Jiahui Han, Beijing (CN); Song Yang, Beijing (CN); and Yujie Liu, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/613,039
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jan. 29, 2021, PCT No. PCT/CN2021/074483
§ 371(c)(1), (2) Date Nov. 19, 2021,
PCT Pub. No. WO2022/160282, PCT Pub. Date Aug. 4, 2022.
Prior Publication US 2023/0090555 A1, Mar. 23, 2023
Int. Cl. G02F 1/1343 (2006.01); G02F 1/1335 (2006.01)
CPC G02F 1/134309 (2013.01) [G02F 1/13439 (2013.01); G02F 1/133514 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An array substrate, comprising: a base substrate, a first electrode, an insulating dielectric layer and a second electrode stacked in sequence; wherein the second electrode is provided with at least one hollow hole, and the hollow hole is in a shape of convex polygon, circle or ellipse;
wherein the hollow hole comprises first hollow holes, and a distance between two adjacent first hollow holes is in a range of 2 μm to 4 μm; and
the hollow hole further comprises a second hollow hole, and the second hollow hole is disposed close to an outer edge of the second electrode; a distance between the second hollow hole and an adjacent first hollow hole is smaller than a distance between two adjacent first hollow holes.