US 11,899,064 B2
Scan architecture for interconnect testing in 3D integrated circuits
Sandeep Kumar Goel, Dublin, CA (US); Yun-Han Lee, Boashan Township (TW); Saman M. I. Adham, Kanata (CA); and Marat Gershoig, Ottawa (CA)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 13, 2022, as Appl. No. 18/080,680.
Application 16/724,787 is a division of application No. 15/171,531, filed on Jun. 2, 2016, granted, now 10,539,617.
Application 18/080,680 is a continuation of application No. 16/724,787, filed on Dec. 23, 2019, granted, now 11,549,984.
Prior Publication US 2023/0113905 A1, Apr. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/28 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/2896 (2013.01); G01R 31/31703 (2013.01); G01R 31/318513 (2013.01); G01R 31/318536 (2013.01); G01R 31/318538 (2013.01); G01R 31/318552 (2013.01); G01R 31/318566 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first die having disposed thereon a first plurality of latches; and
a second die having disposed thereon a second plurality of latches, wherein:
each latch of the first plurality of latches on said first die operatively couple to a respective latch in the second plurality of latches on said second die,
a scan path comprises a closed loop comprising each of said first and second plurality of latches, wherein the scan path goes consecutively through a first latch in the first plurality of latches in the first die, a second latch in the second plurality of latches in the second die, a third latch in the second plurality of latches in the second die, and a fourth latch in the first plurality of latches the first die,
the first latch and the fourth latch are adjacent to each other in the first die, and
the second latch and the third latch are adjacent to each other in the second die.