US 11,899,063 B2
Generating multiple pseudo static control signals using on-chip JTAG state machine
Mudasir Shafat Kawoosa, Srinagar (IN); and Rajesh Mittal, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 29, 2022, as Appl. No. 17/809,616.
Application 17/809,616 is a continuation of application No. 16/920,806, filed on Jul. 6, 2020, granted, now 11,408,936.
Application 16/920,806 is a continuation of application No. 16/039,067, filed on Jul. 18, 2018, granted, now 10,739,402, issued on Aug. 11, 2020.
Application 16/039,067 is a continuation of application No. 15/226,898, filed on Aug. 2, 2016, granted, now 10,060,979, issued on Aug. 28, 2018.
Prior Publication US 2022/0326303 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31713 (2013.01); G01R 31/31723 (2013.01); G01R 31/31727 (2013.01); G01R 31/318385 (2013.01); G01R 31/318547 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a scan chain; and
a test access port (TAP) coupled to the scan chain, the test access port includes:
a first circuit configured to:
transmit a first signal based on a state of the first circuit;
receive a test pattern;
modify a state associated with the first circuit based on the received test pattern; and
transmit a second signal based on the modified state; and
a second circuit coupled to the first circuit and configured to:
receive the first and second signals; and
generate control signals to the scan chain based on a sequence of the first and second signals.