| CPC H10N 50/10 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |

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1. A method for manufacturing a semiconductor structure, comprising:
depositing a dielectric layer over a top surface of a first metal layer;
forming a bottom electrode via (BEVA) hole penetrating the dielectric layer;
forming a diffusion barrier layer and a flowable film over the dielectric layer and in the BEVA hole, wherein a portion of the diffusion barrier layer overlapping a top surface of the dielectric layer is exposed through the flowable film;
employing an etching operation to remove the diffusion barrier layer at a faster rate than the flowable film until a top surface of the diffusion barrier layer is lower than a top surface of the dielectric layer; and
forming a magnetic tunneling junction (MTJ) structure over the top surface of the dielectric layer and covering the diffusion barrier layer.
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