US 12,225,811 B2
Display apparatus and electronic apparatus
Tetsuo Minami, Tokyo (JP); and Katsuhide Uchino, Kanagawa (JP)
Assigned to JDI DESIGN & DEVELOPMENT G.K., Tokyo (JP)
Filed by JDI DESIGN & DEVELOPMENT G.K., Tokyo (JP)
Filed on Dec. 24, 2021, as Appl. No. 17/561,856.
Application 17/561,856 is a continuation of application No. 17/002,710, filed on Aug. 25, 2020, granted, now 11,239,436.
Application 17/002,710 is a continuation of application No. 16/686,988, filed on Nov. 18, 2019, granted, now 10,784,453, issued on Sep. 22, 2020.
Application 16/686,988 is a continuation of application No. 16/351,742, filed on Mar. 13, 2019, granted, now 10,516,122, issued on Dec. 24, 2019.
Application 16/351,742 is a continuation of application No. 16/046,219, filed on Jul. 26, 2018, granted, now 10,276,814, issued on Apr. 30, 2019.
Application 16/046,219 is a continuation of application No. 15/666,523, filed on Aug. 1, 2017, granted, now 10,069,092, issued on Sep. 4, 2018.
Application 15/666,523 is a continuation of application No. 15/430,731, filed on Feb. 13, 2017, granted, now 9,755,168, issued on Sep. 5, 2017.
Application 15/430,731 is a continuation of application No. 13/302,624, filed on Nov. 22, 2011, granted, now 9,608,215, issued on Mar. 28, 2017.
Claims priority of application No. 2010-276940 (JP), filed on Dec. 13, 2010.
Prior Publication US 2022/0123239 A1, Apr. 21, 2022
Int. Cl. G09G 3/32 (2016.01); G09G 3/325 (2016.01); G09G 3/3266 (2016.01); G09G 3/3283 (2016.01); H10K 50/84 (2023.01); H10K 59/131 (2023.01); H10K 77/10 (2023.01); G02F 1/1333 (2006.01); G09G 3/3225 (2016.01); H10K 102/00 (2023.01)
CPC H10K 77/111 (2023.02) [G09G 3/325 (2013.01); G09G 3/3266 (2013.01); G09G 3/3283 (2013.01); H10K 50/84 (2023.02); H10K 59/131 (2023.02); G02F 1/133305 (2013.01); G09G 3/3225 (2013.01); G09G 2320/045 (2013.01); G09G 2380/02 (2013.01); H10K 2102/311 (2023.02); Y02E 10/549 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display apparatus, comprising:
a first substrate;
a pixel array comprising a plurality of pixels on the first substrate;
a first peripheral circuit on a first end of the first substrate configured to drive the pixel array, wherein the first substrate comprises a first foldable region between the pixel array and the first peripheral circuit;
a second peripheral circuit on a second end of the first substrate configured to drive the pixel array, wherein the pixel array is between the second peripheral circuit and the first peripheral circuit, and the first substrate comprises a second foldable region between the pixel array and the second peripheral circuit;
a first wiring section over the first foldable region of the first substrate, wherein the first wiring section is between the pixel array and the first peripheral circuit, and the pixel array is between the second peripheral circuit and the first wiring section;
a second wiring section over the second foldable region of the first substrate, wherein the second wiring section is between the pixel array and the second peripheral circuit;
a first folding jig on a rear face of the first wiring section;
a second folding jig on a rear face of the second wiring section; and
a second substrate, wherein the pixel array is between the first substrate and the second substrate, and a length of the second substrate, in a non-folded state of the display apparatus, in a first direction parallel to a top surface of the first substrate is less than a length of the first substrate, in the non-folded state of the display apparatus, in the first direction.