US 12,225,784 B2
Display substrate including shielding pattern overlapping reset transistor, method for manufacturing the same, and display device
Tinghua Shang, Beijing (CN); Yi Zhang, Beijing (CN); Tingliang Liu, Beijing (CN); Linhong Han, Beijing (CN); Huijuan Yang, Beijing (CN); Shun Zhang, Beijing (CN); and Yu Wang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/418,136
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Aug. 31, 2020, PCT No. PCT/CN2020/112668
§ 371(c)(1), (2) Date Jun. 24, 2021,
PCT Pub. No. WO2022/041238, PCT Pub. Date Mar. 3, 2022.
Prior Publication US 2022/0336562 A1, Oct. 20, 2022
Int. Cl. H10K 59/131 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/35 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/131 (2023.02) [H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/126 (2023.02); H10K 59/351 (2023.02); H10K 59/353 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A display substrate, comprising: a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein the plurality of sub-pixels includes:
an initialization signal line pattern, at least part of the initialization signal line pattern extending along a first direction;
a reset signal line pattern, at least part of the reset signal line pattern extending along the first direction;
a power signal line pattern, at least a part of the power signal line pattern extending along a second direction, the second direction intersecting the first direction;
a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor and a first reset transistor, and a gate electrode of the first reset transistor is electrically connected to the reset signal line pattern, a first electrode of the first reset transistor is electrically connected to the initialization signal line pattern, and a second electrode of the first reset transistor is electrically connected to a gate electrode of the driving transistor; and
a shielding pattern, wherein the shielding pattern is electrically connected to the power signal line pattern, an orthographic projection of the shielding pattern on the pixel unit, and the shielding pattern is electrically connected to the power signal line pattern through a connection hole;
wherein the second electrode of the first reset transistor is electrically connected to the gate electrode of the driving transistor through a fifth conductive connection portion, an orthographic projection of the connection hole on the substrate is located between an orthographic projection of the gate electrode of the first reset transistor on the substrate and an orthographic projection of the fifth conductive connection portion on the substrate in plan view.