US 12,225,781 B2
Array substrate and display apparatus
Yu Feng, Beijing (CN); Libin Liu, Beijing (CN); and Jiangnan Lu, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/788,605
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Aug. 30, 2021, PCT No. PCT/CN2021/115249
§ 371(c)(1), (2) Date Jun. 23, 2022,
PCT Pub. No. WO2022/188374, PCT Pub. Date Sep. 15, 2022.
Claims priority of application No. PCT/CN2021/080326 (WO), filed on Mar. 11, 2021.
Prior Publication US 2024/0215344 A1, Jun. 27, 2024
Int. Cl. G09G 3/3233 (2016.01); G09G 3/32 (2016.01); H10K 59/124 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/124 (2023.02) [G09G 3/32 (2013.01); G09G 3/3233 (2013.01); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, and a first connecting pad in a first signal line layer, the first connecting pad connecting the second electrode of the transistor and the second electrode of the first reset transistor;
wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
the active layer of the driving transistor comprises a first semiconductor material; and
the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
wherein the first connecting pad is connected to the second electrode of the transistor through a first via extending through at least a passivation layer, and is connected to the second electrode of the first reset transistor through a second via extending through at least the passivation layer and the insulating layer.