| CPC H10K 59/122 (2023.02) [H10K 59/1201 (2023.02)] | 18 Claims | 

| 
               1. A display substrate comprising a base substrate, a thin film transistor array layer located on the base substrate, a planarization layer covering the thin film transistor array layer, and a first electrode and a pixel definition layer located on the planarization layer, the pixel definition layer defining a plurality of pixel openings, each pixel opening comprising a first edge and a second edge adjacent to each other, the pixel definition layer comprising a first pixel definition layer parallel to the first edge and a second pixel definition layer parallel to the second edge in a display region of the display substrate, wherein a surface of the first pixel definition layer away from the base substrate is located at a level lower than a surface of the second pixel definition layer away from the base substrate, a groove parallel to the first edge is arranged in a surface of the planarization layer away from the base substrate, at least a part of the first pixel definition layer is arranged in the groove, the pixel definition layer further comprises a third pixel definition layer surrounding the display region, and a surface of the third pixel definition layer away from the base substrate is located at a level not lower than the surface of the second pixel definition layer away from the base substrate; 
            wherein the display substrate comprises a plurality of first electrodes separate from each other, and an orthogonal projection of a gap between adjacent first electrodes onto the base substrate is within an orthogonal projection of a groove bottom of the groove onto the base substrate. 
               |