US 12,225,767 B2
Array substrate, method for manufacturing the same, display panel and display device
Yuanjie Xu, Beijing (CN); and Yue Long, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Nov. 24, 2021, as Appl. No. 17/535,146.
Claims priority of application No. 202110278051.0 (CN), filed on Mar. 15, 2021.
Prior Publication US 2022/0293692 A1, Sep. 15, 2022
Int. Cl. H10K 59/121 (2023.01); H10K 59/12 (2023.01); H10K 59/131 (2023.01); H10K 59/65 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/121 (2023.02) [H10K 59/131 (2023.02); H10K 59/65 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 19 Claims
OG exemplary drawing
 
1. An array substrate, comprising a display region, wherein the display region comprises an opening region, and the array substrate comprises:
a base substrate;
a driving circuitry structure comprising a transparent conductive layer for forming a transparent line, and an active layer and a plurality of metal layers for forming a plurality of pixel driving circuitries, the transparent conductive layer being laminated on and in contact with the active layer, and/or the transparent conductive layer being laminated on and in contact with one metal layer; and
an anode layer arranged at a side of the driving circuitry structure away from the base substrate and comprising a plurality of anodes, each anode arranged at the opening region being electrically coupled to a corresponding pixel driving circuitry via the transparent line;
wherein the plurality of metal layers comprises a first gate metal layer arranged at a side of the active layer away from the base substrate, a second gate metal layer arranged at a side of the first gate metal layer away from the active layer, a first source/drain metal layer arranged at a side of the second gate metal layer away from the first gate metal layer, and a second source/drain metal layer arranged at a side of the first source/drain metal layer away from the second gate metal layer; and
the driving circuitry structure further comprises a first insulation layer arranged between the active layer and the first gate metal layer, a second insulation layer arranged between the first gate metal layer and the second gate metal layer, a third insulation layer arranged between the second gate metal layer and the first source/drain metal layer, a fourth insulation layer arranged between the first source/drain metal layer and the second source/drain metal layer, and a fifth insulation layer arranged between the second source/drain metal layer and the anode layer.