| CPC H10D 84/853 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/405 (2025.01); H10D 62/822 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] | 19 Claims |

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1. A semiconductor device, comprising:
a substrate;
a fin protruding from the substrate;
a plurality of nanosheets on the fin;
a source/drain on the fin;
a gate on the fin, the gate including a main gate portion on the plurality of nanosheets, and a plurality of sub-gate portions between the plurality of nanosheets and the fin; and
a plurality of insulating spacers on sidewalls of the plurality of sub-gate portions; and
a plurality of air spacers between the plurality of insulating spacers and the source/drain,
wherein the source/drain have a pair of sidewalls opposite each other, and
wherein a first portion of each side surface of the pair of sidewalls of the source/drain is a concave surface and a second portion of each side surface of the pair of sidewalls of the source/drain is a convex surface, the first portion extending in a vertical direction from a level of an upper surface of an insulating spacer to a level of a lower surface of the insulating spacer and the second portion extending in the vertical direction from a level of a middle portion of the insulating spacer to a level of a middle portion of an adjacent insulating spacer.
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