US 12,225,740 B2
Dual metal silicide structures for advanced integrated circuit structure fabrication
Jeffrey S. Leib, Beaverton, OR (US); Srijit Mukherjee, Portland, OR (US); Vinay Bhagwat, Hillsboro, OR (US); Michael L. Hattendorf, Portland, OR (US); and Christopher P. Auth, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 7, 2024, as Appl. No. 18/435,609.
Application 18/435,609 is a continuation of application No. 17/967,511, filed on Oct. 17, 2022, granted, now 11,961,767.
Application 17/967,511 is a continuation of application No. 17/068,121, filed on Oct. 12, 2020, granted, now 11,508,626, issued on Nov. 22, 2022.
Application 17/068,121 is a continuation of application No. 16/516,693, filed on Jul. 19, 2019, granted, now 10,840,151, issued on Nov. 17, 2020.
Application 16/516,693 is a continuation of application No. 15/859,357, filed on Dec. 30, 2017, granted, now 10,796,968, issued on Oct. 6, 2020.
Claims priority of provisional application 62/593,149, filed on Nov. 30, 2017.
Prior Publication US 2024/0178071 A1, May 30, 2024
Int. Cl. H01L 21/8238 (2006.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 10/00 (2023.01); H10D 1/47 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/017 (2025.01) [H01L 21/0337 (2013.01); H01L 21/28247 (2013.01); H01L 21/28568 (2013.01); H01L 21/3086 (2013.01); H01L 21/31105 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/76816 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H10B 10/12 (2023.02); H10D 1/474 (2025.01); H10D 30/6213 (2025.01); H10D 30/6219 (2025.01); H10D 30/792 (2025.01); H10D 30/795 (2025.01); H10D 62/151 (2025.01); H10D 64/015 (2025.01); H10D 64/689 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/0167 (2025.01); H10D 84/0177 (2025.01); H10D 84/0181 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first semiconductor device, the first semiconductor device comprising:
first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode, respectively, the first and second semiconductor source or drain regions comprising a layer comprising germanium; and
a first metal silicide layer directly on the layer comprising germanium of the first and second semiconductor source or drain regions, wherein the first metal silicide layer comprises nickel, platinum and silicon; and
a second N-type semiconductor device, the second semiconductor device comprising:
third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode, respectively; and
a second metal silicide layer directly on the third and fourth semiconductor source or drain regions, respectively, wherein the second metal silicide layer comprises titanium and silicon, the second metal silicide layer having a different composition than the first metal silicide layer.