US 12,225,738 B2
Method for manufacturing nitride semiconductor device and nitride semiconductor device
Hirotaka Otake, Kyoto (JP); and Kentaro Chikamatsu, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Appl. No. 17/787,945
Filed by ROHM CO., LTD., Kyoto (JP)
PCT Filed Jan. 15, 2021, PCT No. PCT/JP2021/001163
§ 371(c)(1), (2) Date Jun. 22, 2022,
PCT Pub. No. WO2021/149599, PCT Pub. Date Jul. 29, 2021.
Claims priority of application No. 2020-010249 (JP), filed on Jan. 24, 2020.
Prior Publication US 2023/0043312 A1, Feb. 9, 2023
Int. Cl. H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/47 (2006.01); H01L 29/66 (2006.01)
CPC H10D 30/4732 (2025.01) [H10D 30/015 (2025.01); H10D 30/6738 (2025.01); H10D 30/675 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 62/8503 (2025.01); H10D 64/64 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A method for manufacturing nitride semiconductor device comprising:
a first step of forming a first nitride semiconductor layer that constitutes an electron transit layer, a second nitride semiconductor layer that constitutes an electron supply layer, and a gate layer material film that is a material film of a nitride semiconductor gate layer containing an acceptor type impurity in that order above a substrate;
a second step of forming, on the gate layer material film, a gate electrode film that is a material film of a gate electrode;
a third step of selectively etching the gate electrode film to form the gate electrode of a ridge shape;
a fourth step of selectively etching the gate layer material film to form the semiconductor gate layer of a ridge shape with the gate electrode disposed at a width intermediate portion of a front surface thereof; and
a fifth step of forming a passivation film such as to cover an exposed front surface of the second nitride semiconductor layer, side surfaces and an exposed front surface of the nitride semiconductor gate layer, and side surfaces of the gate electrode; and
wherein the third step includes a first etching step for forming a first portion from an upper end to a thickness direction intermediate portion of the gate electrode and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion of the gate electrode and
the exposed front surface of the second nitride semiconductor layer, the side surfaces and the exposed front surface of the nitride semiconductor gate layer, and the side surfaces of the gate electrode are covered by the same passivation film.