US 12,225,735 B2
Selector for memory device
Hung-Ju Li, Hsinchu (TW); Kuo-Pin Chang, Hsinchu (TW); Yu-Wei Ting, Taipei (TW); Ching-En Chen, Chiayi (TW); and Kuo-Ching Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 7, 2022, as Appl. No. 17/833,907.
Prior Publication US 2023/0397440 A1, Dec. 7, 2023
Int. Cl. H10B 63/00 (2023.01)
CPC H10B 63/24 (2023.02) 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first metallic layer;
a first low bandgap ovonic threshold switching (OTS) layer disposed in direct contact with the first metallic layer;
a high bandgap OTS layer disposed adjacent to the first low bandgap OTS layer and in direct contact with the first low bandgap OTS layer;
a second low bandgap OTS layer disposed adjacent to the high bandgap OTS layer and in direct contact with the high bandgap OTS layer; and
a second metallic layer disposed adjacent to the second low bandgap OTS layer and in direct contact with the second low bandgap OTS layer; and, wherein the first metallic layer, the first low bandgap OTS layer, the high bandgap OTS layer, the second low bandgap OTS layer and the second metallic layer forming a phase change element arranged to have a threshold voltage to operate with a corresponding leakage current.