| CPC H10B 51/30 (2023.02) [H10B 51/20 (2023.02)] | 20 Claims |
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1. A memory device comprising:
a plurality of gate layer stacks, wherein each gate layer stack of the plurality of gate layer stacks comprises a gate electrode layer and one or more electrically insulating layers;
one or more channel structures extending through the plurality of gate layer stacks,
wherein the plurality of gate layer stacks and the one or more channel structures correspond to a plurality of field-effect transistor based memory cells of the memory device,
wherein a first field-effect transistor based memory cell of the plurality of field-effect transistor based memory cells comprises:
a first gate layer portion of a first gate layer stack of the plurality of gate layer stacks;
a first channel portion of a channel structure of the one or more channel structures;
a spontaneously-polarizable portion; and
a first floating gate,
wherein the spontaneously-polarizable portion and the first floating gate are disposed between the first gate layer portion and the first channel portion, and
wherein a height of the spontaneously-polarizable portion is less than a height of the first floating gate when measured along an axis parallel to a longitudinal axis of the one or more channel structures.
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