US 12,225,731 B2
Memory array contact structures
Chih-Yu Chang, New Taipei (TW); Meng-Han Lin, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); Bo-Feng Young, Taipei (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/818,638.
Application 17/818,638 is a division of application No. 17/125,435, filed on Dec. 17, 2020, granted, now 11,653,500.
Claims priority of provisional application 63/044,101, filed on Jun. 25, 2020.
Prior Publication US 2022/0384348 A1, Dec. 1, 2022
Int. Cl. H10B 51/20 (2023.01); G11C 11/22 (2006.01); H01L 23/535 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [G11C 11/2255 (2013.01); H01L 23/535 (2013.01); H01L 29/66787 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 51/10 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a multi-layer stack comprising a plurality of word lines;
depositing a memory film on a sidewall of the multi-layer stack;
forming a first channel region and a second channel region on the memory film;
depositing a contact layer on the memory film, on the first channel region, and on the second channel region;
depositing a conductive material on the contact layer;
etching a first trench in the contact layer and conductive material, wherein the trench separates a first portion of the contact layer and a first portion of the conductive material from a second portion of the contact layer and a second portion of the conductive material, wherein the first portion contacts the first channel region and the second portion contacts the second channel region; and
depositing an insulating material in the first trench.