US 12,225,730 B2
Three-dimensional semiconductor memory device and electronic system including the same
Sehoon Lee, Seoul (KR); and Byoungil Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 16, 2021, as Appl. No. 17/377,840.
Claims priority of application No. 10-2020-0131991 (KR), filed on Oct. 13, 2020.
Prior Publication US 2022/0115390 A1, Apr. 14, 2022
Int. Cl. H10B 43/35 (2023.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/46 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/35 (2023.02) [H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/46 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor memory device, comprising:
a substrate comprising a cell array region and an extension region;
a plurality of stack structures which extend in a first direction and comprise a plurality of gate electrodes stacked on the substrate;
a plurality of vertical structures which penetrate the stack structures on the cell array region;
a mold structure on a portion of the extension region;
a first support structure which extends in the first direction between the stack structures;
a plurality of second support structures which penetrate the stack structures on the extension region and are spaced apart in a second direction from the first support structure, the second direction intersecting the first direction; and
a third support structure which surrounds the mold structure in a plan view,
wherein respective top surfaces of ones of the second support structures and a top surface of the third support structure are higher than top surfaces of ones of the vertical structures with respect to the substrate defining a base reference level, and
wherein a bottom surface of the first support structure, respective bottom surfaces of the second support structures and a bottom surface of the third support structure are between a bottom surface of a lowermost one of the gate electrodes and a bottom surface of ones of the plurality of vertical structures.