US 12,225,728 B2
Method for fabricating semiconductor memory device including channel posts of different shapes
Sung Wook Jung, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 24, 2023, as Appl. No. 18/306,092.
Application 18/306,092 is a continuation of application No. 16/931,048, filed on Jul. 16, 2020, granted, now 11,672,122.
Claims priority of application No. 10-2020-0047218 (KR), filed on Apr. 20, 2020.
Prior Publication US 2023/0262982 A1, Aug. 17, 2023
Int. Cl. H10B 43/30 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/30 (2023.02) [H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
alternately stacking a plurality of insulating interlayers that are alternately stacked with a plurality of sacrificial layers to form a stack structure;
selectively etching the stack structure to form a gate separation layer configured to separate an uppermost sacrificial layer among the plurality of sacrificial layers;
forming a plurality of channel posts through the stack structure, channel posts among the plurality of the channel posts adjacent to the gate separation layer having a first curved portion and a second curved portion having a curvature different from a curvature of the first curved portion in a planar view; and
replacing the plurality of sacrificial layers by a plurality of gate conductive layers.