CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/40 (2023.02)] | 4 Claims |
1. A method of manufacturing a memory device, the method comprising:
providing a stacked structure having a cell region and a slimming region;
forming vertical channel structures in the stacked structure in the cell region;
forming support structures, in the stacked structure in the slimming region simultaneously with forming the vertical channel structures, wherein the support structures have the same structure as the vertical channel structures; and
performing a slimming process so that the stacked structure in the slimming region and the support structures have a stepped structure.
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