US 12,225,725 B2
Semiconductor devices and manufacturing methods of the same
So Hyeon Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 11, 2022, as Appl. No. 17/650,700.
Application 17/650,700 is a continuation of application No. 16/386,740, filed on Apr. 17, 2019, granted, now 11,251,192.
Claims priority of application No. 10-2018-0066815 (KR), filed on Jun. 11, 2018.
Prior Publication US 2022/0165749 A1, May 26, 2022
Int. Cl. H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 29/41775 (2013.01); H01L 29/42324 (2013.01); H01L 29/4234 (2013.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 43/30 (2023.02); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/31111 (2013.01); H01L 21/31155 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/66545 (2013.01); H01L 29/7883 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of gate conductive regions spaced apart from each other and stacked in a direction perpendicular to an upper surface of a substrate, the plurality of gate conductive regions including a first gate conductive region and a plurality of second gate conductive regions;
a plurality of gate insulating regions, each surrounded at least partially by each of the plurality of second gate conductive regions;
a contact plug filling a contact hole passing through the first gate conductive region and the plurality of gate insulating regions, and electrically connected to the first gate conductive region;
a first dielectric layer horizontally extended along the first gate conductive region, and covering an upper surface and a lower surface of the first gate conductive region; and
a plurality of second dielectric layers horizontally extended along the plurality of second gate conductive regions, and covering upper surfaces and lower surfaces of the plurality of second gate conductive regions,
wherein a distance from an adjacent edge of the first gate conductive region to the contact hole is different from a distance from an adjacent edge of each of the plurality of second gate conductive regions to the contact hole,
wherein a side surface of the contact plug has protruding portions protruding outwardly toward the plurality of gate conductive regions, and
wherein the plurality of second dielectric layers cover side surfaces of the plurality of second gate conductive regions facing the contact plug, and the first dielectric layer exposes a side surface of the first gate conductive region facing the contact plug.