US 12,225,724 B2
Methods of manufacturing a semiconductor device
Hwanyeol Park, Seoul (KR); Sejin Kyung, Seoul (KR); Ilwoo Kim, Yongin-si (KR); Minwoo Lee, Yongin-si (KR); and Youngho Jeung, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 20, 2021, as Appl. No. 17/505,842.
Claims priority of application No. 10-2021-0052923 (KR), filed on Apr. 23, 2021.
Prior Publication US 2022/0344367 A1, Oct. 27, 2022
Int. Cl. H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
alternately and repeatedly forming a first insulation layer and a first sacrificial layer on a substrate to form a mold layer;
forming a sacrificial layer structure on the mold layer, the sacrificial layer structure including an etch stop layer and a second sacrificial layer sequentially stacked;
forming a hard mask on the sacrificial layer structure;
etching the sacrificial layer structure and the mold layer by a dry etching process using the hard mask as an etching mask to form a channel hole exposing an upper surface of the substrate, and form a recess on a sidewall of the second sacrificial layer, the sidewall of the second sacrificial layer being adjacent to the channel hole;
providing layers over the recess in the channel hole to form a memory channel structure; and
replacing the first sacrificial layer with a gate electrode.