US 12,225,723 B2
Non-volatile memory device
Der-Tsyr Fan, Taoyuan (TW); I-Hsin Huang, Taoyuan (TW); and Tzung-Wen Cheng, New Taipei (TW)
Assigned to IOTMEMORY TECHNOLOGY INC., Taipei (TW)
Filed by IOTMEMORY TECHNOLOGY INC., Taipei (TW)
Filed on Mar. 30, 2022, as Appl. No. 17/709,370.
Prior Publication US 2023/0320088 A1, Oct. 5, 2023
Int. Cl. H10B 41/44 (2023.01); H10B 41/10 (2023.01); H10B 41/48 (2023.01)
CPC H10B 41/44 (2023.02) [H10B 41/10 (2023.02); H10B 41/48 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising at least one memory cell, wherein the at least one memory cell comprises:
a substrate;
a stacked structure, disposed on the substrate and comprising a gate dielectric layer, an assist gate, and an insulation layer stacked in order;
a tunneling dielectric layer, disposed on the substrate at one side of the stacked structure;
a floating gate, disposed on the tunneling dielectric layer and comprising an uppermost edge and a curved sidewall;
a control gate structure, covering the curved sidewall of the floating gate; and
an erase gate structure, covering the floating gate and the control gate structure, wherein the uppermost edge of the floating gate is embedded in the erase gate structure, and a portion of the erase gate structure is disposed above the floating gate and the control gate structure.