CPC H10B 41/41 (2023.02) [H10B 41/10 (2023.02); H10B 41/50 (2023.02); H01L 25/0655 (2013.01)] | 20 Claims |
1. A non-volatile memory device, comprising:
a source region and a drain region disposed in a channel length direction on a substrate;
a flash cell, comprising a floating gate and a control gate, disposed between the source region and the drain region;
a selection gate disposed between the source region and the flash cell;
a selection line connecting the selection gate;
a word line connecting the control gate;
a common source line connected to the source region;
a bit line connected to the drain region;
a control gate pick up structure, connected to the control gate, comprising a plurality of floating gate poly-silicon patterns; and
a control gate contact plug disposed between the plurality of floating gate poly-silicon patterns.
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