US 12,225,721 B2
Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
John D. Hopkins, Meridian, ID (US); and Nancy M. Lomeli, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 16, 2022, as Appl. No. 17/841,925.
Application 17/841,925 is a division of application No. 16/894,519, filed on Jun. 5, 2020, granted, now 11,393,835.
Prior Publication US 2022/0310641 A1, Sep. 29, 2022
Int. Cl. H10B 41/27 (2023.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 41/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A memory array comprising strings of memory cells, comprising:
a conductor tier comprising conductor material;
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers;
insulator-material bodies in and longitudinally-along opposing sides of individual of the memory blocks in a lowest of the conductive tiers, the insulator-material bodies being spaced relative one another longitudinally-along the memory blocks; and
conductive material in the lowest conductive tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.