| CPC H10B 12/488 (2023.02) [H01L 29/401 (2013.01); H01L 29/4236 (2013.01); H10B 12/00 (2023.02); H10B 12/056 (2023.02); H10B 12/36 (2023.02); H01L 29/413 (2013.01)] | 18 Claims |
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1. A manufacturing method of a semiconductor device, comprising:
providing a semiconductor substrate having a shallow trench isolation (STI) structure and a plurality of active regions disposed in parallel;
forming a first wordline trench structure in the semiconductor substrate;
forming a first sacrificial layer at a bottom of the first wordline trench structure;
filling the first wordline trench structure located in the active regions by epitaxial growth;
forming a first insulation layer covering a top of the semiconductor substrate and the first wordline trench structure in the STI structure and sealing the first wordline trench structure;
forming a second wordline trench structure and a fin-type structure in the active regions, a depth of the second wordline trench structure being less than that of the first wordline trench structure, and a vertical projection of the second wordline trench structure completely overlapping with a vertical projection of the first sacrificial layer;
removing the first sacrificial layer to form a wordline tunnel in the semiconductor substrate connected with the first wordline trench structure; and
filling the first wordline trench structure, the second wordline trench structure and the wordline tunnel to form a buried wordline structure surrounding the fin-type structure;
wherein the semiconductor substrate is a silicon-on-insulator (SOI) substrate, comprising a silicon material layer, a back substrate and an oxide material layer sandwiched between the silicon material layer and the back substrate, and all of the STI structure, the plurality of active regions and the buried wordline structure are landing on a same horizontal top surface of the oxide material layer.
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