| CPC H10B 12/34 (2023.02) [H10B 12/053 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02)] | 10 Claims |
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1. A method of manufacturing a semiconductor structure, comprising:
providing a substrate;
forming multiple initial active pillars on the substrate, wherein the multiple initial active pillars are arranged in an array;
forming a gate layer between the initial active pillars, wherein the gate layer is connected to sidewalls of each initial active pillar;
forming a first dielectric layer on the gate layer and on the initial active pillars;
forming, in the first dielectric layer, openings extending along a row arrangement direction of the initial active pillars; wherein a projection of one of the openings on the substrate partially overlaps with a projection of each of the initial active pillars in the same row on the substrate, and another projection, which does not overlap with the projection of one of the openings on the substrate, of two adjacent initial active pillars in the same row on the substrate is located on two sides of one of the openings respectively;
removing the initial active pillar exposed in each opening to form an active pillar; and removing the gate layer exposed in each opening to form an isolation trench and a word line, wherein two adjacent active pillars located in the same row are located on two sides of the isolation trench; and
forming an isolation structure in the isolation trench, wherein the isolation structure extends out of the isolation trench and covers the gate layer and the active pillar, the isolation structure comprises a first side and a second side that are provided opposite to each other, the isolation structure extends along an arrangement direction of the active pillars in the same row, such that two adjacent active pillars in the same row are separated on two sides of the isolation structure;
wherein after the step of providing a substrate, and before the step of forming multiple initial active pillars on the substrate, the method of manufacturing a semiconductor structure further comprises:
forming multiple bit line structures in the substrate, wherein the multiple bit line structures are arranged at intervals on the substrate along a row direction of the active pillars, each of the bit line structures comprises a bit line and a bit line contact portion provided on the bit line, and a top surface of the bit line contact portion is flush with a top surface of the substrate;
wherein the step of forming multiple initial active pillars on the substrate comprises:
sequentially forming a second dielectric layer and a first mask layer that are stacked on the substrate;
removing part of the first mask layer and part of the second dielectric layer, to form multiple second grooves arranged at intervals, wherein one of the second grooves exposes a top surface of one bit line structure; and
forming the initial active pillar in each second groove, the initial active pillar comprising a channel region as well as a source and a drain, the source and the drain being provided on two ends of the channel region respectively.
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