US 12,225,711 B2
Semiconductor device comprising wiring layer over driver circuit
Shunpei Yamazaki, Tokyo (JP); and Yasuhiko Takemura, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Oct. 23, 2023, as Appl. No. 18/382,551.
Application 18/382,551 is a continuation of application No. 17/402,723, filed on Aug. 16, 2021, granted, now 11,805,637.
Application 17/402,723 is a continuation of application No. 16/933,041, filed on Jul. 20, 2020, granted, now 11,139,301, issued on Oct. 5, 2021.
Application 16/933,041 is a continuation of application No. 16/292,667, filed on Mar. 5, 2019, granted, now 10,763,261, issued on Sep. 1, 2020.
Application 16/292,667 is a continuation of application No. 15/701,499, filed on Sep. 12, 2017, granted, now 10,249,626, issued on Apr. 2, 2019.
Application 15/701,499 is a continuation of application No. 15/148,000, filed on May 6, 2016, granted, now 9,786,668, issued on Oct. 10, 2017.
Application 15/148,000 is a continuation of application No. 14/336,118, filed on Jul. 21, 2014, granted, now 9,337,345, issued on May 10, 2016.
Application 14/336,118 is a continuation of application No. 13/344,921, filed on Jan. 6, 2012, granted, now 8,811,064, issued on Aug. 19, 2014.
Claims priority of application No. 2011-005401 (JP), filed on Jan. 14, 2011.
Prior Publication US 2024/0049449 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 12/00 (2023.01); G11C 5/10 (2006.01); G11C 11/401 (2006.01); G11C 11/408 (2006.01); H01L 21/84 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 49/02 (2006.01)
CPC H10B 12/31 (2023.02) [G11C 5/10 (2013.01); G11C 11/401 (2013.01); G11C 11/4085 (2013.01); H01L 21/84 (2013.01); H01L 23/528 (2013.01); H01L 23/53228 (2013.01); H01L 27/0688 (2013.01); H01L 27/1207 (2013.01); H01L 28/91 (2013.01); H01L 29/7869 (2013.01); H10B 12/05 (2023.02); H10B 12/30 (2023.02); H10B 12/48 (2023.02); H10B 12/50 (2023.02)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first layer comprising a transistor;
a second layer provided over the first layer, the second layer comprising a wiring layer; and
a third layer provided over the second layer, the third layer comprising an insulating layer,
wherein a first conductive layer is provided over the first layer,
wherein part of a side surface of the first conductive layer is in contact with the second layer,
wherein a second conductive layer is provided in a first opening provided in the second layer and in a second opening provided in the third layer,
wherein a third conductive layer is provided over the second conductive layer,
wherein the second conductive layer has a region in contact with a top surface of the first conductive layer and a region in contact with the side surface of the first conductive layer,
wherein, in a cross-sectional view, the second conductive layer has a first region overlapping with the first conductive layer, a second region, and a third region,
wherein, in the cross-sectional view, the second region and the third region do not overlap with the first conductive layer and sandwich the first region,
wherein, in a plan view, the second conductive layer has a region extending from the first region along one direction, and
wherein the third conductive layer has a region in contact with a top surface of the region extending from the first region.